3D Integrated Circuits and Chiplet-Based Architectures for High-Performance and Scalable Computing Systems

Abstract

The monolithic system-on-chip (SoC) design can become increasingly power density
limited, interconnect congested, yield limited and thermally limited in high-performance
computing platforms. The use of 3D ICs and chiplet-based architecture has become
effective due to their heterogeneous integration and the ability to scale the system in a
better way. Nevertheless, they should be practically adopted with proper architectural
subdivision, interconnection design and thermal optimization at various levels of the
design. In this paper, a scalable 3D chiplet architecture is introduced, which is backed
by a cross-layer design methodology of high-performance and data-intensive computing
systems. The suggested solution integrates the workload-based chiplet partitioning
schemes, the implementation of the hierarchical workload interconnect schemes (both
vertical and horizontal) with the thermal-aware placement schemes to achieve the
controlled performance, power, and temperature limits. Analytical models are created
to model system power consumption, interconnect latency and energy efficiency to allow
the architecture trade-off to be evaluated quantitatively. The analysis of the simulation
evidence shows that the suggested architecture can result in significant enhancement
in throughput and energy efficiency besides being characterised by significantly lower
peak operating temperature relative to the traditional monolithic and 2.5D interposer
based systems. The findings demonstrate the benefits of chiplet disaggregation and
3D integration to the scalability of emerging workloads that have increased compute
needs. The general impression gained illustrates that the presented framework offers
valuable design and a feasible background into next-generation VLSI systems with
regards to 3D IC and chiplet-based integration.