Design of Ultra-Low-Power VLSI Architectures for Edge-Intelligent IoT Applications

Abstract

The high rate of growth in edge-intelligent Internet of things (IoT) devices has made
the need to have an ultra-low-power VLSI architecture, capable of running on-device
intelligence within strict energy, area, and latency requirements a pressing concern.
Traditionally based microcontroller and accelerator based designs can not always be
optimally energy efficient because of non-flexible architecture, poor data movement
and minimal runtime flexibility. This paper develops the design of ultra-low-power
VLSI architecture explicitly designed to support the edge-intelligent IoT applications,
where both the architectural-level innovation and the circuit-level power optimization
are applied. The architecture being proposed incorporates the use of a data-adaptive,
lightweight and compute subsystem, aggressive data reuse, an energy optimized
memory hierarchy, and fine-grained power management (such as dynamic voltage
scaling and frequency scaling and selective power gating). An integrated approach
of architecture-circuit co-design to reduce dynamic and leakage power with real
time inference capability is embraced. Its implementation is based on a traditional
CMMS technology flow and does tests on representative edge-intelligence workloads.
Demonstrated in experiment, these show significant energy per operation and overall
power consumption as well as better energy-delay efficiency than the standard low
power VLSI baselines. The proposed architecture shows a scalable and silicon-realizable
solution to next-generation simplistic sensory systems on the edges, which is expected
to offer an attractive way of making energy-restrained systems based on a continuing
intelligent sensory platform.